Controlling power consumption in a data processing apparatus

ABSTRACT

A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus.

This application is the U.S. national phase of International ApplicationNo. PCT/GB2006/002418, filed 29 Jun. 2006, the entire contents of whichis hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to techniques for controlling powerconsumption in a data processing apparatus.

BACKGROUND OF THE INVENTION

It is known to provide a data processing apparatus having logic elementswhich can communicate with each other over a communication path.Communication between the logic elements occurs via transfers which maybe issued from one logic element (referred to herein as the initiatorlogic element) to another logic element (referred to herein as therecipient logic element) via the communication path. Often, the dataprocessing apparatus will include multiple logic elements, andindividual logic elements may be able to act as initiator logic elementsfor certain transfers and recipient logic elements for other transfers.In such a data processing apparatus, it is known to provide bus logicfor providing the required communication paths between the various logicelements. One example of such bus logic is an interconnect circuit whichprovides multiple connections over which communication paths can beestablished between particular initiator logic elements and particularrecipient logic elements.

As data processing apparatus increase in complexity, the number of logicelements provided within the data processing apparatus increase, andthis increases the complexity of the bus logic. Typically bus logic mayprovide a larger number of paths for routing transfers between thevarious logic elements connected to the bus logic, and due to thegeneral desire to keep such data processing apparatus as small aspossible, the physical conductors laid out within the data processingapparatus to form these paths are becoming thinner and thinner.Typically the paths are formed from a metal such as copper, and inrecent designs the individual conductive lines are getting so thin thatresistance along those lines is becoming problematic. In particular, asthe resistance and capacitance increases, the time taken for signals topropagate along the paths increases, reducing the performance of thedata processing apparatus.

With the aim of seeking to combat this problem, it is known to providebuffer circuits within individual communication paths which are used toassist in speeding the propagation of the signals along thecommunication path. In particular, by the use of such buffer circuits,individual communication paths are broken down into smaller sections andthe buffer circuits are used to amplify the signals as they arepropagated from one section to another along the communication path. Asa result, this improves the speed of propagation of signals along thecommunication path.

However, the introduction of such buffer circuits introduces a newproblem, namely an increase in power consumption due to leakage currentswithin the buffer circuits, most notably substrate and gate leakagecurrents within the individual transistors forming the buffer circuits.In some implementations, power consumption is a very important issue,and in such implementations it is clearly desirable to seek to reducethe effects of such leakage current.

A number of known techniques have been developed for seeking to reducesuch leakage current. For example, the article “Leakage-AwareInterconnect for On-Chip Network” by Yuh-Fang Tsai et al, Proceedings ofthe Design, Automation and Test in Europe Conference and Exhibition(Date 2005), pages 230 to 231, describes a number of leakage-awareinterconnect designs where a mixture of high threshold voltage andnominal threshold voltage transistors are used to form the buffers, thisgiving rise to a buffer design that has less leakage current. To furtherreduce leakage current this article describes the use of a special sleepsignal which in a standby mode pulls the input to a buffer circuit downto a low voltage level, which is found to further reduce leakagecurrent.

The article “A New Threshold Voltage Assignment Scheme for RuntimeLeakage Reduction in On-Chip Repeaters” by Saumil Shah et al, ICCD 2004,pages 138 to 143, also describes the use of mixed threshold voltagetransistors to reduce leakage power consumption in buffers (referred toas “repeaters” in that article).

The article “Low-Leakage Repeaters for NoC Interconnects” by ArkadiyMorgenshtein et al, ISCAS 2005, describes several leakage reductiontechniques for buffer circuits for Network-on-Chip (NoC) interconnects.Again, mixed threshold voltage designs are described where some of thetransistors in the buffer have a low threshold voltage and some have ahigh threshold voltage. A design described employs header and footersleep transistors associated with each buffer circuit (or alternatesbetween header sleep transistors and footer sleep transistors from onebuffer circuit to the next), which are driven by a clock signal toenable individual buffer circuits to be turned on or off, therebyreducing leakage current.

Whilst such an approach can produce power consumption savings in certaintypes of systems, for example systems where components are laid out in aregular and structured manner with the clock signal paths being laid outin close proximity to the payload data paths, the effectiveness of theapproach is ultimately limited by the distribution of the clock signal,and by the granularity with which the clock signal can be gated forparticular blocks of the system. For example, the buffer circuits do notactually retain state and accordingly do not need to be clocked. As aresult, in many systems it is highly likely that a suitable clock signalwill not be provided in physical proximity to the buffer circuits, andsignificant adaptation to the layout design would be required tofacilitate the routing of a clock signal to those buffer circuits. Inaddition, if the clock signal were to be used to turn the buffercircuits on and off, then typically additional clock buffering would berequired. Further, any individual clock signal will typically be used tocontrol a particular block of components within the system andaccordingly it would not be possible to use that clock signal to controlonly a particular communication path within the system. Accordingly,only a relatively coarse granularity of control can be achieved.

Accordingly, it would be desirable to provide an improved technique forreducing power consumption resulting from leakage current within buffercircuits provided within communication paths of a data processingapparatus.

SUMMARY OF THE INVENTION

Viewed from a first aspect, the present invention provides a dataprocessing apparatus comprising: a plurality of logic elements, at leastone of the logic elements being an initiator logic element forinitiating transfers, and at least one of the logic elements being arecipient logic element for receiving transfers; a communication pathcoupling an initiator logic element with a recipient logic element,payload data the subject of a transfer being passed over thecommunication path from the initiator logic element to the recipientlogic element; the communication path having at least one buffer circuitprovided therein for propagating at least the payload data along thecommunication path; and a power control circuit associated with said atleast one buffer circuit, responsive to a control signal indicative ofwhether the payload data on the communication path is valid, to causethe associated at least one buffer circuit to enter a power saving statewhen the control signal indicates that the payload data is not valid,the control signal being derived from at least one pre-existing signalassociated with the transfer.

In accordance with the present invention, a power control circuit isprovided which receives a control signal that is derived from at leastone pre-existing signal associated with the transfer. The use of apre-existing signal avoids the need to generate a separate dedicatedcontrol signal for the power control circuit, and thereby avoids theadditional complexities that would be involved in generating and routingsuch a dedicated signal. Further, since the pre-existing signal used isone that is associated with the transfer, it can be used specifically toachieve power control within the communication path over which thepayload data of that transfer is passed. In particular, in accordancewith the present invention, if the control signal indicates that thepayload data is not valid, then the power control circuit causes the atleast one buffer circuit in that communication path to enter a powersaving state.

Hence, by deriving the control signal from a pre-existing signal that isassociated with the transfer, fine granularity of control can beachieved, since the value of the control signal can be specifiedindependently for each communication path. Further, since thepre-existing signal used is associated with the transfer, it willtypically be routed in close physical proximity to the actual payloaddata of that transfer, and accordingly the routing complexities arereduced when compared with using a system-wide signal such as a clocksignal. Another disadvantage of using a clock signal, which isalleviated by the present invention, is that additional buffering of theclock signal would be required if the clock signal were to be used tocontrol power, and this would partially offset any power savings due tothe resultant leakage power loss from that additional clock bufferinglogic. As a result, the approach of the present invention is a much moreflexible and efficient approach, since it can be used in a wide varietyof different designs of data processing apparatus.

In one embodiment, the communication path has multiple buffer circuitsarranged in series along the communication path, and the control signalis passed along a path having a buffer element provided therein inassociation with each buffer circuit, whereby the time at which eachbuffer circuit enters or exits the power saving state is staggered withrespect to other of said buffer circuits. Such an approach isparticularly useful when exiting the power saving state, as itinherently smoothes out the power-on surge that might otherwise beobserved if each of the buffer circuits exited the power saving state atexactly the same time.

The buffer elements used to buffer the control signal may be permanentlypowered. However, alternatively, each such buffer element may beprovided within the associated buffer circuit, and as a result may besubjected to the power saving state when the control signal indicatesthat the payload data is not valid. Such an approach will give rise to afurther reduction in leakage current, since the leakage current thatmight otherwise be observed within the buffer elements is reduced whenthe power saving state is entered. When the power saving state isexited, the staggering of the turn on times of each of the buffercircuits is further spread out, due to the delay in not only propagatingthe control signal along the path through each buffer element, but alsodue to the time taken to turn each buffer element on when exiting thepower saving state. Hence, depending on a balance to be struck betweenoverall reduction in leakage current and speed of turn on when exitingthe power saving state, it can be decided whether to place the controlsignal buffer elements within the buffer circuit subjected to the powersaving state by the power control circuit, or whether instead to notsubject those buffer elements to such a power saving state but insteadleave them on permanently.

The power control circuit can be arranged in a variety of ways. However,in one embodiment, a separate power control circuit is provided for eachbuffer circuit. In a typical implementation, the communication path usedto carry the payload data may be many bits wide, for example a 32-bitcommunication path, and in such instances an associated buffer circuitwill typically comprise a separate physical buffer for each bit acrossthe width of the communication path, each such buffer typicallycomprising multiple transistors. As a result, the logic within the powercontrol circuit needs to be relatively large, such that when theassociated buffer circuit is powered up, the power control circuit canprovide the necessary power to all of the individual buffers within thebuffer circuit. As a result, in such implementations it may bepreferable to provide a separate power control circuit for each buffercircuit rather than sharing a particular power control circuit amongstmultiple buffer circuits.

In one embodiment, each buffer element is provided within the associatedpower control circuit. In such embodiments, a cell can be defined thatincludes the power control circuit for a particular buffer circuit andan associated buffer element used to buffer the control signal. When thecontrol signal is in fact provided directly by a particular pre-existingsignal associated with the transfer, such an approach provides a greatdeal of flexibility, since at the layout stage of the design, it can bedecided whether to merely provide a standard buffer element used tobuffer the pre-existing signal as it is routed along the communicationpath, or whether instead to use one of the above-mentioned cells whichincludes that buffer element, but additionally includes the powercontrol circuit necessary to facilitate the use of a power saving statefor the associated buffer circuit. If the use of the power saving stateis desired for a particular buffer circuit, then the new cell will beused, and if for a particular buffer circuit power saving is notrequired, then the standard buffer element can instead be used.

The control signal may take a variety of forms. It may for example bederived from multiple pre-existing signals associated with the transfer.However, in one embodiment, the control signal is a pre-existing validsignal associated with the transfer and asserted by the initiator logicelement when the payload data is valid. In one particular embodiment,once the valid signal is asserted, the initiator logic element isoperable to keep the valid signal asserted until receipt of a signalfrom the recipient logic element causes a handshake to take place.Accordingly, the use of the valid signal as the control signal in suchembodiments is particularly beneficial, since when the valid signal isasserted, the various buffer circuits within the communication path canbe brought out of the power saving state reliably in a staggered manner,safe in the knowledge that they will not have to be put back into thepower saving state until after the transfer has occurred.

The signal received from the recipient logic element can take a varietyof forms. In one embodiment, the signal from the recipient logic elementis a ready signal that is asserted by the recipient logic element whenthat recipient logic element is available to receive the payload data,the recipient logic element being arranged such that once the readysignal is asserted it will not be de-asserted until the payload data hasbeen received, the valid signal as received by the power control circuitbeing qualified by the ready signal so that the power saving state isonly exited when the valid signal indicates that the payload data isvalid and the ready signal indicates that the recipient logic element isavailable to receive the payload data. Hence, if the ready signal can bearranged to continue to be asserted until the payload data has beenreceived, then qualifying the valid signal with such a ready signalreduces the amount of time that the power saving state is exited for.

One bus protocol that uses valid and ready signals is the AXI (AdvancedeXtensible Interface) protocol developed by ARM Limited, Cambridge,United Kingdom, which requires that an initiator logic element issues avalid signal when it wishes to initiate a transfer, and that this validsignal is held stable until the completion of a handshake that takesplace when a ready signal is asserted by the recipient logic element.Whilst there is a requirement for the valid signal to be held stableuntil completion of the handshake (a valid signal conforming to thisrequirement sometimes being referred to as a “sticky” valid signal), theready signal is not constrained in this way. Instead, in the generalcase, the ready signal may be asserted and de-asserted in any clockcycle depending on the internal state of the recipient logic element.Indeed, some recipient logic elements may even wait for a valid signalto be asserted before they issue a ready signal. Accordingly, the abovedescribed process for reducing the amount of time that the power savingstate is exited from may not be able to be used in all situations.However, in some situations, it may be possible to place a constraint ona particular recipient logic element such that once it has asserted theready signal it will continue to assert the ready signal until itreceives the payload data (a ready signal having this property alsobeing referred to herein as a “sticky” ready signal). Indeed, in U.S.patent application Ser. No. 10/862,812, owned by the applicant of thepresent application (the contents of which are incorporated herein byreference), a storage element is described which can temporarily storethe transfer data of a transfer, and that storage element is arrangedsuch that it does use a sticky ready signal. Accordingly, in situationswhere the recipient logic element is provided by such a storage element,then the qualifying of the valid signal with such a ready signal wouldgive rise to further power savings. In particular, in such a situation,the power saving state would only need to be exited for a single clockcycle per transfer.

The power control circuit can take a variety of forms. However, in oneembodiment the power control circuit comprises one or more headertransistors located between the at least one buffer circuit and a powersupply to the at least one buffer circuit. Such header transistors willtypically be larger than the transistors used within the buffer circuit,so as to ensure that those header transistors can provide the powerrequired to turn on the various transistors within the buffer circuitwhen that buffer circuit is not in the power saving state. Further, suchheader transistors typically have a relatively high threshold voltage toreduce leakage current from those header transistors.

In one embodiment, the data processing apparatus has a pipelinedarchitecture and the communication path is provided within a pipelinestage traversable by the payload data in a single clock cycle, thecontrol signal being propagated one cycle ahead of its associatedpayload data, whereby said at least one buffer circuit enters or exitsthe power saving state ahead of the time the payload data reaches thatbuffer circuit. Accordingly, in situations where latency is a keyconcern, such an approach can be used to reduce the latency in exitingthe power saving state by ensuring that each buffer circuit along thecommunication path exits the power saving state ahead of the time thepayload data reaches that buffer circuit.

In one embodiment, a single power saving state is provided, namely astate where the power control circuit causes the power supply to thebuffer circuit to be removed, thereby causing the buffer circuit nodesto drift to ground potential. In this state, there is minimum substrateand gate current leakage. However, in alternative embodiments, more thanone possible power saving state may be provided. In particular, in oneembodiment, when the control signal indicates that the payload data isnot valid, the power control circuit is operable to select based on atleast one further control signal one of a plurality of available powersaving states for the associated at least one buffer circuit to enter.Such an approach hence requires an additional control signal to berouted to each power control circuit, but does provide extra flexibilitywith regard to choice of power saving state.

In one embodiment, the power control circuit is further operable toreceive an override signal which when set causes the power saving stateto be disabled. Accordingly, by such an approach, the operation of thepower control circuit can effectively be overridden by the overridesignal as and when required. In modern data processing apparatus,Intelligent Energy Management (IEM) techniques are being adopted, whichenable voltage supplies within the apparatus and/or frequency of theclock signal to be altered with the aim of achieving better energyconsumption. In such embodiments, the IEM circuitry could be used togenerate the override signal in certain situations where it was feltappropriate not to use the power saving state.

In one embodiment, the power control circuit comprises a plurality oftransistors arranged in parallel, when the control signal indicates thatthe payload data is not valid, all of said transistors being turned offto disconnect the buffer circuit from a power supply to thereby causethe buffer circuit to enter a power down power saving state, unless theat least one further control signal is set in which event a subset ofthe transistors are turned on to thereby cause the buffer circuit toenter a retention power saving state. Hence, as an alternative to a fullpower down mode of operation, a retention mode of operation can be usedwhere the voltage on the buffer circuit nodes may droop, but can beretained above a particular logic threshold value. In some situations,this may result in less energy wastage and/or power supply spikes if theduration of the power saving state is relatively short. Hence, in somesuch embodiments, it may be appropriate to use the retention powersaving state for a relatively short period of time, and thereafterproceed to the fill power down state if the power saving state has notin the interim been exited. As with the override signal, IEM controllogic could be used to generate the further control signal used toselect between the full power down and the retention state.

The initiator logic element and the recipient logic element can take avariety of forms. Indeed, for some transfers the initiator logic elementmay be a master device whilst the recipient logic element is a slavedevice, whilst for other transfers the initiator logic element may be aslave device whilst the recipient logic element is a master device.Further, either one or both of the initiator logic elements may bestorage elements used to temporarily store at least the payload dataduring its transfer between a master device and a slave device. Inparticular, in situations where the path between a master device and aslave device is of such a length that it cannot be traversed in a singleclock cycle, storage elements can be placed within that path in order toseparate the path into a number of communication paths which can betraversed in a single clock cycle.

The communication path between the initiator logic element and therecipient logic element can take a variety of forms. For example it maybe a dedicated point-to-point link between a particular initiator logicelement and a particular recipient logic element. However, in oneembodiment, the communication path is provided within interconnect logicused to provide a plurality of paths for interconnecting the pluralityof logic elements.

Viewed from a second aspect, the present invention provides bus logicoperable to interconnect a plurality of logic elements to enable datatransfers to occur, at least one of the logic elements being aninitiator logic element for initiating transfers, and at least one ofthe logic elements being a recipient logic element for receivingtransfers, the bus logic comprising: a communication path coupling aninitiator logic element with a recipient logic element, payload data thesubject of a transfer being passed over the communication path from theinitiator logic element to the recipient logic element; at least onebuffer circuit within the communication path for propagating at leastthe payload data along the communication path; and a power controlcircuit associated with said at least one buffer circuit, responsive toa control signal indicative of whether the payload data on thecommunication path is valid, to cause the associated at least one buffercircuit to enter a power saving state when the control signal indicatesthat the payload data is not valid, the control signal being derivedfrom at least one pre-existing signal associated with the transfer.

Viewed from a third aspect, the present invention provides a method ofcontrolling power consumption within a data processing apparatus havinga plurality of logic elements, at least one of the logic elements beingan initiator logic element for initiating transfers, and at least one ofthe logic elements being a recipient logic element for receivingtransfers, the method comprising the steps of: passing payload data thesubject of a transfer over a communication path from an initiator logicelement to a recipient logic element; using at least one buffer circuitprovided within the communication path to propagate at least the payloaddata along the communication path; and responsive to a control signalindicative of whether the payload data on the communication path isvalid, causing the associated at least one buffer circuit to enter apower saving state when the control signal indicates that the payloaddata is not valid, the control signal being derived from at least onepre-existing signal associated with the transfer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described further, by way of example only,with reference to embodiments thereof as illustrated in the accompanyingdrawings, in which:

FIG. 1 is a block diagram illustrating the use of a bus interconnectblock within a data processing apparatus;

FIG. 2 is a block diagram illustrating the provision of buffer circuitswithin communication paths provided by the interconnect block of FIG. 1in accordance with one embodiment of the present invention;

FIG. 3 is a diagram illustrating the provision of power control circuitsin association with buffer circuits of a communication path inaccordance with one embodiment of the present invention;

FIG. 4 is a diagram illustrating the provision of power control circuitsin association with buffer circuits of a communication path inaccordance with an alternative embodiment of the present invention;

FIG. 5 is a diagram schematically illustrating an alternative embodimentfor the power control circuit of FIG. 3 in accordance with oneembodiment of the present invention; and

FIG. 6 is a block diagram schematically illustrating how the validsignal may in one embodiment of the present invention be qualified by aready signal issued by a storage element forming a recipient logic unitwithin a communication path.

DESCRIPTION OF EMBODIMENTS

For the purposes of describing an embodiment of the present invention, acommunication path coupling an initiator logic element with a recipientlogic element is considered to be provided within an interconnect blockof a data processing apparatus used to interconnect multiple master andslave devices. FIG. 1 illustrates a particular example of such a dataprocessing apparatus.

FIG. 1 illustrates a data processing apparatus in the form of aSystem-on-Chip (SoC), which may be used within a device such as apersonal organiser, a mobile phone, a television set-top box, etc. TheSoC design 100 has a plurality of logic elements 120, 130, 140, 160,170, 180 that are interconnected by an arrangement of buses. The actualinterconnection of these buses is specified within an interconnect blockor circuit 150. The interconnect block 150 includes a matrix of pathswhich provides for the interconnection of multiple bus master devicesand bus slave devices within the SoC 100. Hence, each master device 120,130, 140 may be connected to corresponding buses 125, 135, 145,respectively, whilst each slave device 160, 170, 180 may also beconnected to corresponding buses 165, 175, 185, respectively, with theinterconnect block 150 defining how these various buses areinterconnected.

The buses interconnecting the various elements will typically operate inaccordance with a specified bus protocol, and hence for example mayoperate in accordance with the “Advanced Microcontroller BusArchitecture” (AMBA) specification developed by ARM Limited, Cambridge,United Kingdom.

Accordingly, it will be appreciated that the interconnect block 150 willdescribe a complex arrangement of interconnections between variousmaster and slave devices. This complex arrangement may include a numberof unidirectional channels of information. Within one or more of thesechannels there may be connections which are shared between multiplepaths, and for which the interconnect block needs to perform arbitrationin order to ensure that at any point in time only one transfer's data isbeing routed over such a shared connection.

In order to seek to meet a requirement for a chosen characteristic ofthe bus interconnect block, such as an improvement in a timingcharacteristic, one or more storage elements (also referred to herein asregister slices) may be inserted within the interconnect block. Given achannel of information, a register slice can be used to insert aregister between a source and destination on each of the informationsignals within the channel.

Within a system such as that described with reference to FIG. 1, theinterconnect logic can be seen to couple a number of master and slavedevices to enable transactions to be performed. Each transactionconsists of an address transfer from a master device to a slave device(via any intervening register slices) and one or more data transfersbetween that master device and that slave device (again via anyintervening register slices). For a write transaction, these datatransfers will pass from the master device to the slave device (in someimplementations there will additionally be a write response transferfrom the slave device to the master device), whilst for a readtransaction these data transfers will pass from the slave device to themaster device.

The interconnect logic provides a plurality of connection paths forcoupling the various master devices and slave devices, and the way inwhich the various transfers are routed via those connection paths willbe dependent on the bus protocol employed within the interconnect logic.One known type of bus protocol is the non-split transaction protocol,such as is employed within a data processing apparatus having an AHB busdesigned in accordance with the AHB bus protocol developed by ARMLimited, Cambridge, United Kingdom. In accordance with such a non-splittransaction protocol, there is a fixed timing relationship between theaddress transfer of a transaction and the subsequent one or more datatransfers of that transaction. In particular, the data transfer startsin the cycle following that in which the address is transferred.

As interconnect logic increases in complexity, due to the need tosupport the interconnection of a larger number of master and slavedevices, then another type of bus protocol has been developed known as asplit transaction protocol. In accordance with such a split transactionprotocol, the plurality of connection paths within the interconnectlogic provide at least one address channel for carrying addresstransfers and at least one data channel for carrying data transfers. Anexample of such a split transaction protocol is the AXI (AdvancedeXtensible Interface) protocol developed by ARM Limited, Cambridge,United Kingdom. The AXI protocol provides a number of channels overwhich information and data can be transferred, these channels comprisinga read address channel for carrying address transfers of readtransactions, a write address channel for carrying address transfers ofwrite transactions, a write data channel for carrying data transfers ofwrite transactions, a read data channel for carrying data transfers ofread transactions, and a write response channel for returningtransaction status information to the master device at the end of awrite transaction, such transaction status information indicating forexample whether the transaction completed successfully, or whether anerror occurred, etc. Use of such a split transaction protocol canincrease the performance of a system compared with a similar systemusing a non-split transaction protocol.

Whilst embodiments of the present invention are applicable to variousdifferent bus protocols, for the purposes of describing a particularembodiment of the present invention, it will be assumed that theinterconnect logic of FIG. 1 uses the above-mentioned AXI protocol.

As the interconnect logic increases in complexity due to the increase inthe number of master and slave devices to be supported, and given thegeneral desire to keep the apparatus as small as possible, the actualphysical wires providing the various connection paths within theinterconnect logic are becoming thinner and thinner. This has resultedin an increase in the resistance and capacitance observed along thosepaths, which has the effect of slowing down the speed of transfer ofsignals along those paths. As described earlier, buffer circuits can beintroduced into those paths with the aim of amplifying the signals atvarious points along the path and as a result increasing the speed oftransfer of the signals. However, these buffer circuits can give rise toundesirable leakage current which adversely affects the powerconsumption of the apparatus. In accordance with embodiments of thepresent invention, power control circuitry is provided in associationwith each such buffer circuit with the aim of seeking to reduce leakagecurrent.

FIG. 2 is a diagram schematically illustrating a connection path from amaster device 200 to a slave device 250 via an intervening registerslice 230. The connection path can hence be seen to consist of twocommunication paths, a first communication path 260 being between themaster device 200 and the register slice 230, and a second communicationpath 270 being between the register slice 230 and the slave device 250.In the example shown in FIG. 2, the first communication path 260 has twobuffer circuits 205, 215 provided therein, and the second communicationpath 270 has a single buffer circuit 235 provided therein. In accordancewith embodiments of the present invention each buffer circuit 205, 215,235 has a power control circuit 210, 220, 240 associated therewith,which receive as an input a control signal derived from at least onepre-existing signal associated with the transfer occurring over thecommunication path.

In the example illustrated in FIG. 2, the transfer is assumed to bepassing from the master device 200 to the slave device 250, andaccordingly may be a write address transfer over the write addresschannel, a data transfer over the write data channel, or a read addresstransfer over the read address channel. Each channel has a pair ofhandshake signals referred to as ready and valid signals that are usedto coordinate the transfer of data. The valid signal is asserted whenthe sender has driven valid payload data onto the channel payloadsignals. This payload data will typically consist of the actual databeing transferred (e.g. an address on an address channel, or write/readdata on a write/read channel, respectively) along with certain controlinformation, for example used in identifying the type of transfer. Theready signal is asserted when the receiver is ready to receive payloaddata. A handshake occurs when the valid and ready signals are assertedin the same clock cycle. The AXI protocol requires that once the validsignal has been asserted, it cannot be de-asserted until a handshake hasoccurred.

In accordance with such an embodiment of the present invention, thecontrol signal used as an input to the power control circuits 210, 220,240 is the valid signal asserted by the sender. Accordingly, the powercontrol circuits 210, 220 in FIG. 2 receive the valid signal output bythe master device 200, which when asserted will indicate that validpayload data is being output by the master device 200. Similarly, thepower control circuit 240 in FIG. 2 will receive a valid signal issuedby the register slice 230, which will be asserted when the registerslice outputs valid payload data.

FIG. 3 is a diagram schematically illustrating the buffer circuits andassociated power control circuits that may be used within acommunication path in accordance with one embodiment of the presentinvention. In FIG. 3, the individual bit lines forming the communicationpath are shown, and the payload portion of the communication path willtypically consist of multiple bit lines, three of which are shown inFIG. 3. Each buffer circuit will contain a separate buffer for each bitline, and accordingly a first buffer circuit consists of the buffers345, 300, 305, 310, a second buffer circuit consists of the buffers 350,315, 320, 325, and a further buffer circuit consists of the buffers 355,330, 335, 340. In this embodiment, it will be noted that the validsignal is also propagated along the communication path via each buffercircuit, through use of the buffers 345, 350, 355.

In accordance with this embodiment of the present invention, a powercontrol cell is provided in association with each buffer circuit, whichin this embodiment includes logic that enables the associated buffercircuit to be placed into a power saving state, including the bufferelement used to buffer the valid signal. Accordingly, considering thefirst buffer circuit formed by buffers 345, 300, 305, 310, a powercontrol cell 360 is provided, which incorporates the buffer element 345,and an inverter 365 and header transistor 370 for performing therequired power control function. The header transistor 370 is a highthreshold voltage and high drive (i.e. large) header transistor, whichwhen turned on will provide sufficient power to drive all of thetransistors in the individual buffer elements 345, 300, 305, 310 of theassociated buffer circuit.

It will be appreciated that when the valid signal is at a low voltagelevel (indicating that the payload data is not valid), then the inverter365 will cause a logic one level to be supplied to the header transistor370 which will turn that header transistor off, thereby de-coupling thebuffer elements 345, 300, 305, 310 of the buffer circuit from theirsupply voltage VDD. As a result, the nodes of the individual bufferelements drift to ground potential with no further power beingdissipated, and in this state there is minimum substrate and gateleakage.

When the valid signal is asserted at a logic one level, indicating thatthe payload data is valid, then the inverter 365 will cause a logic zerolevel to be provided to the header transistor 370, causing the headertransistor to turn on. In this state, the header transistor 370 providesa low resistance connection to VDD and the individual buffer elements345, 300, 305, 310 of the buffer circuit then behave normally, to causethe valid signal and associated payload data to be propagated over thecommunication path.

As discussed earlier, the header transistor 370 has to be large enoughto supply all the power for the buffers without saturating. The size ofthe header transistor is in the embodiment of FIG. 3 kept down by usinga separate header transistor for each separate buffer circuit along thecommunication path of the channel. Accordingly, a second power controlcell is formed by inverter 375 and header transistor 380, along with theassociated buffer element 350, and a further power control cell isformed by the inverter 385 and header transistor 390, along with theassociated buffer element 355.

The use of the separate power control circuitry for each buffer circuithas the further benefit of reducing the power surge that would otherwiseoccur when the header transistors are switched on. In particular, aswill be seen from FIG. 3, when the valid signal is asserted, the headertransistor 380 will not be turned on until the header transistor 370 hasturned on and the associated buffer element 345 has then driven thevalid signal from its output. Likewise, the header transistor 390 willnot turn on until the header transistor associated with the precedingbuffer circuit has turned on and the valid signal has been propagatedfrom the buffer element of that buffer circuit. This delay hence causesthe power to be applied in sequence along the channel, spreading thepower surge over the channel delay.

It should be noted that whilst in FIG. 3 the various buffer elementsforming a particular buffer circuit are shown in columns, such buffercircuits are not themselves a layout cell but rather are a grouping ofindividual buffer elements connected to a single “virtual” VDD supplyprovided by the associated power control circuit. In reality, theindividual buffers forming any particular buffer circuit will bedispersed within the interconnect as dictated by the exigencies of thelayout. Hence, as an example, the buffer elements 345, 300, 305, 310forming the first buffer circuit may not be located in a distinct groupwithin the layout of the interconnect but may in fact be more dispersedwithin the interconnect. Additionally, whilst for ease of illustrationFIG. 3 shows an example implementation having the same number of buffersin every bit line, some bit lines may have fewer or more buffers as aresult of placement and timing decisions.

FIG. 4 illustrates an alternative embodiment of the present inventionwhere the buffer elements used to buffer the valid signal are notsubjected to the power saving state. Each power control cell in thisembodiment hence just comprises the inverter and associated headertransistor. Accordingly, a first power control cell 400 consists of theinverter 365 and header transistor 370. Similarly, a second powercontrol cell is formed by the inverter 375 and associated headertransistor 380, and a further power control cell is formed by theinverter 385 and header transistor 390. The valid signal is received bythese power control cells in the same way as discussed earlier withreference to the power control cells of FIG. 3, but in this instance thebuffer circuit associated with the power control cell comprises only thebuffer elements forming the payload part of the communication path. Incontrast, the buffer elements 405, 410, 420 used to buffer the validsignal are permanently powered, and are not subjected to the powersaving state. Whilst this will result in those buffer elements producingleakage current even when no valid payload data exists, there will be areduction in the time taken to exit the power saving state when thevalid signal is asserted. For example, the header transistor 380 nolonger needs to wait for header transistor 370 to turn on, but insteadis merely delayed with respect to the turning on of the headertransistor 370 by the inherent delay in propagation of the valid signalalong the path through buffer 405. Accordingly, the power surge is stillspread out since the header transistor in each separate power cell willturn on at slightly different times, but overall time taken to exit thepower saving state across the communication path will be less, therebyreducing latency.

FIG. 5 illustrates an alternative embodiment of power control cell thatmay be used instead of the power control cell illustrated in FIG. 3. Inthis embodiment, each power control cell 500 consists of a plurality ofheader transistors 505, 510, 515, 520, 525 arranged in parallel. Inaddition to the valid signal, this power control cell 500 receives twofurther signals, namely an override signal and a retention state signal.The group of transistors 510, 515, 520, 525 acts like the headertransistor illustrated in FIG. 3, in that when the valid signal isasserted high, that signal will be propagated via OR gate 530 to theinverter 535, to cause a logic zero value to be provided to each of thetransistors 510, 515, 520, 525, thereby turning those transistors on andcausing the buffers in the associated buffer circuit, including thebuffer element 540 associated with the valid signal, to operatenormally. However, when the valid signal is de-asserted, then theinverter 535 will cause a logic one value to be provided to thetransistors 510, 515, 520, 525, thereby essentially disconnecting theassociated buffer circuit from its supply voltage VDD. As a result, eachof the internal nodes within each buffer element will drift to groundpotential, thereby reducing leakage current in the power saving state.

However, in accordance with the FIG. 5 embodiment, a retention signalcan also be input, which when at a logic zero level (indicating that aretention state is not required), will cause the transistor 505 to beturned off (by virtue of the retention signal being inverted prior toinput to transistor 505). However, if the retention state is set to alogic one value, indicating that a retention state is desired, then thiswill cause the transistor 505 to be turned on. Accordingly, even if thevalid signal is low, this means that the buffer elements of theassociated buffer circuit are still coupled to VDD through the singletransistor 505. The single transistor 505 will not produce enough powerto allow all of the buffer elements to operate normally, and as a resultthe voltage at the internal nodes within each buffer element will droop.However, rather than drifting to ground potential, the current passingthrough the transistor 505 will be sufficient to hold these internalnodes above a particular logic threshold value. As a result, when thevalid signal subsequently goes high, and the power saving state isexited, there is likely to be less energy wastage and less powerconsumed than if the retention state were not used. However, in theretention state there will still be some leakage current observed, butless than in the fully on state.

In one particular embodiment, it is envisaged that the retention signalwill be driven by some intelligent energy management (IEM) logicprovided within the data processing apparatus to perform overall energymanagement functions. In one particular embodiment it is envisaged thatthe IEM control logic may be arranged to set the retention state for ashort period whilst the valid signal is not set, such that the initialpower saving state is a retention state. Once that short period hasexpired, then the retention state may be de-asserted, so that the fullpower down state is then entered, assuming that in the interim the validsignal has not been asserted to indicate that the power saving stateshould be exited.

As shown in FIG. 5, the power control circuit also receives an overridesignal, which when set causes the power saving state to be disabled bycausing the transistors 510, 515, 520, 525 to be turned on. Accordingly,by such an approach, the operation of the power control circuit caneffectively be overridden by the override signal as and when required.In one embodiment, the above mentioned IEM logic could be used togenerate the override signal in certain situations where it was feltappropriate not to use the power saving state.

It will be appreciated that the exact number of transistors provided inparallel within the power control cell can be varied, and indeed thereis no requirement for the retention signal to only be routed to a singletransistor. It will also be appreciated that in another variant thebuffer 540 could be omitted from the power control cell 500, such thatthe resultant power control cell could be used as an alternative to thepower control cell 400 illustrated in FIG. 4.

Further, as an alternative to the use of the retention transistor 505,the header transistor, or group of header transistors as shown in FIG.5, can be biased so as not to switch off completely when the validsignal is low, as a result of which the voltage at the internal nodeswill droop but will be held above a particular threshold value.

FIG. 6 illustrates a further embodiment of the present invention, wherethe recipient logic element is a register slice that is able to assert a“sticky” ready signal. Accordingly, when the register slice asserts aready signal indicating that it is available to store transfer data, itwill continue to assert that ready signal until the transfer data hasbeen received. As a result, this ready signal can be used to qualify thevalid signal input to each power control circuit associated with eachbuffer circuit in a communication path.

In FIG. 6, a plurality of power slices 600, 610, 620 are shown within acommunication path, each power slice comprising a power control circuitand its associated buffer circuit. The register slice 630 is arranged toreceive the signals output from the final power slice 620. The logic 640is arranged to logically AND the ready signal issued by the registerslice 630 with the valid signal issued by the initiator logic element ofthe communication path. As a result, an asserted valid signal will onlybe passed on to the power slices 600, 610, 620 when the ready signal hasbeen asserted. Thus, the power saving state will only be exited whenboth the valid signal and the ready signal are asserted, therebyreducing the time that the buffer circuits spend in the active state. Inparticular, the various buffer circuits within the communication pathare only powered up for one cycle per transfer. A register slice such asthat described in FIG. 6 is discussed in more detail in U.S. patentapplication Ser. No. 10/862,812, owned by the applicant of the presentapplication.

It will be appreciated that in alternative embodiments, other recipientlogic elements other than register slices may be able to assert a stickyready signal, and accordingly could be used instead of the registerslice 630 in FIG. 6.

In the above described embodiments of the present invention, the powercontrol circuits only use header transistors, rather than both headerand footer transistors, as it has been found that this gives nearly asmuch power savings as would occur using both header and footertransistors. The internal nodes of the buffer elements of each buffercircuit drift to ground potential when the associated headertransistor(s) is turned off, thus reducing leakage current within eachof those buffer circuits. A further reduction in power consumption isachieved when the valid signal is also gated by a sticky ready signal,such that the buffer circuits only exit the power saving state for onecycle per transfer.

From the above described embodiments of the present invention, it willbe appreciated that a flexible approach for reducing leakage currentwithin buffer circuits provided in communication paths of a dataprocessing apparatus is provided. In particular, a control signalderived from at least one pre-existing signal associated with a transferis used to determine whether to cause a buffer circuit in the associatedcommunication path to enter a power saving state or not. By using apre-existing signal associated with the transfer, the control signal canbe set on a transfer-by-transfer basis, and this hence provides a finelevel of granularity of control over the power saving operation. Inaddition, the use of such a control signal reduces wiring complexity,since typically the pre-existing signal associated with the transferwill already be routed in close proximity to the payload data paths.Further, there is no need to rely on special dedicated power controlsignals.

In particular embodiments of the present invention, no changes arerequired to the register transfer language (RTL) design process, sinceat the layout stage it can be decided whether to include a power controlcell or whether alternatively merely to include a standard bufferelement to buffer the valid signal passed over the particularcommunication path.

Although a particular embodiment has been described herein, it will beappreciated that the invention is not limited thereto and that manymodifications and additions thereto may be made within the scope of theinvention. For example, various combinations of the features of thefollowing dependent claims could be made with the features of theindependent claims without departing from the scope of the presentinvention.

The invention claimed is:
 1. A data processing apparatus comprising: aplurality of logic elements, at least one of the logic elements being aninitiator logic element for initiating transfers, and at least one ofthe logic elements being a recipient logic element for receivingtransfers; a communication path coupling an initiator logic element witha recipient logic element, payload data the subject of a transfer beingpassed over the communication path from the initiator logic element tothe recipient logic element; the communication path having at least onebuffer circuit provided therein for propagating at least the payloaddata along the communication path; a power supply for providing power tosaid at least one buffer circuit; and a power control circuit,associated with said at least one buffer circuit and responsive to acontrol signal indicative of whether the payload data on thecommunication path is valid, configured to cause said at least onebuffer circuit to enter a power saving state by decoupling said at leastone buffer circuit from said power supply when the control signalindicates that the payload data is not valid, the control signal beingderived from at least one pre-existing signal associated with thetransfer.
 2. A data processing apparatus as claimed in claim 1, whereinthe communication path has multiple buffer circuits arranged in seriesalong the communication path, and the control signal is passed along apath having a buffer element provided therein in association with eachbuffer circuit, whereby the time at which each buffer circuit enters orexits the power saving state is staggered with respect to other of saidbuffer circuits.
 3. A data processing apparatus as claimed in claim 2,wherein each said buffer element is provided within the associatedbuffer circuit.
 4. A data processing apparatus as claimed in claim 1,wherein a separate said power control circuit is provided for eachbuffer circuit.
 5. A data processing apparatus as claimed in claim 4,wherein each said buffer element is provided within the associated powercontrol circuit.
 6. A data processing apparatus as claimed in claim 1,wherein the control signal is a pre-existing valid signal associatedwith the transfer and asserted by the initiator logic element when thepayload data is valid.
 7. A data processing apparatus as claimed inclaim 6, wherein once the valid signal is asserted, the initiator logicelement is operable to keep the valid signal asserted until receipt of asignal from the recipient logic element causes a handshake to takeplace.
 8. A data processing apparatus as claimed in claim 7, wherein thesignal from the recipient logic element is a ready signal that isasserted by the recipient logic element when that recipient logicelement is available to receive the payload data, the recipient logicelement being arranged such that once the ready signal is asserted itwill not be de-asserted until the payload data has been received, thevalid signal as received by the power control circuit being qualified bythe ready signal so that the power saving state is only exited when thevalid signal indicates that the payload data is valid and the readysignal indicates that the recipient logic element is available toreceive the payload data.
 9. A data processing apparatus as claimed inclaim 1, wherein the power control circuit comprises one or more headertransistors located between the at least one buffer circuit and a powersupply to the at least one buffer circuit.
 10. A data processingapparatus as claimed in claim 1, wherein the data processing apparatushas a pipelined architecture and the communication path is providedwithin a pipeline stage traversable by the payload data in a singleclock cycle, the control signal being propagated one cycle ahead of itsassociated payload data, whereby said at least one buffer circuit entersor exits the power saving state ahead of the time the payload datareaches that buffer circuit.
 11. A data processing apparatus as claimedin claim 1, wherein when the control signal indicates that the payloaddata is not valid, the power control circuit is operable to select basedon at least one further control signal one of a plurality of availablepower saving states for the associated at least one buffer circuit toenter.
 12. A data processing apparatus as claimed in claim 11, whereinthe power control circuit is further operable to receive an overridesignal which when set causes the power saving state to be disabled. 13.A data processing apparatus as claimed in claim 11, wherein the powercontrol circuit comprises a plurality of transistors arranged inparallel, when the control signal indicates that the payload data is notvalid, all of said transistors being turned off to disconnect the buffercircuit from a power supply to thereby cause the buffer circuit to entera power down power saving state, unless the at least one further controlsignal is set in which event a subset of the transistors are turned onto thereby cause the buffer circuit to enter a retention power savingstate.
 14. A data processing apparatus as claimed in claim 1, whereinthe initiator logic element is a master device, a slave device or astorage element used to temporarily store at least the payload dataduring its transfer between a master device and a slave device.
 15. Adata processing apparatus as claimed in claim 1, wherein the recipientlogic element is a master device, a slave device or a storage elementused to temporarily store at least the payload data during its transferbetween a master device and a slave device.
 16. A data processingapparatus as claimed in claim 1, wherein the communication path isprovided within interconnect logic used to provide a plurality of pathsfor interconnecting the plurality of logic elements.
 17. Bus system forinterconnecting interconnect a plurality of logic elements to enabledata transfers to occur, at least one of the logic elements being aninitiator logic element for initiating transfers, and at least one ofthe logic elements being a recipient logic element for receivingtransfers, the bus system comprising: a communication path coupling aninitiator logic element with a recipient logic element, payload data thesubject of a transfer being passed over the communication path from theinitiator logic element to the recipient logic element; at least onebuffer circuit within the communication path for propagating at leastthe payload data along the communication path; a power supply forproviding power to said at least one buffer circuit; and a power controlcircuit, associated with said at least one buffer circuit and responsiveto a control signal indicative of whether the payload data on thecommunication path is valid, configured to cause said at least onebuffer circuit to enter a power saving state by decoupling said at leastone buffer circuit from said power supply when the control signalindicates that the payload data is not valid, the control signal beingderived from at least one pre-existing signal associated with thetransfer.
 18. A method of controlling power consumption within a dataprocessing apparatus having a plurality of logic elements, at least oneof the logic elements being an initiator logic element for initiatingtransfers, and at least one of the logic elements being a recipientlogic element for receiving transfers, the method comprising the stepsof: passing payload data the subject of a transfer over a communicationpath from an initiator logic element to a recipient logic element; usingat least one buffer circuit provided within the communication path topropagate at least the payload data along the communication path, saiddata processing apparatus including a power supply for supplying powerto said at least one buffer circuit; and causing, in response to acontrol signal indicative of whether the payload data on thecommunication path is valid, said at least one buffer circuit to enter apower saving state by decoupling said at least one buffer circuit fromsaid power supply when the control signal indicates that the payloaddata is not valid, the control signal being derived from at least onepre-existing signal associated with the transfer.